1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a composite semiconductor device having at least one semiconductor device such as a MOS transistor and at least one bipolar transistor both built therein, and a method of making the same.
2. Description of the Prior Art
A composite semiconductor device having two complementary MOS transistors and one bipolar transistor formed on its semiconductor substrate is well known. As a matter of fact, the majority (55%) of such composite type semiconductor device products are rejected because of defective bipolar transistors formed therein. Specifically, bipolar transistors when built in composite semiconductor devices are liable to have insufficient resistance to counter voltage when applied between the heavily doped collector and base regions of the bipolar transistor. This is a significant cause for reduction of output or yield rate.
FIGS. 1A to 1F show how such a composite semiconductor device is produced. Referring to FIG. 1A, a semifabricated product is prepared. It comprises a P-type semiconductor substrate 1 having an N-type epitaxial layer 4 formed on its surface, two adjacent buried regions 2 and 3 heavily doped with P- or N-type impurity in the boundary between the P-type semiconductor substrate 1 and the N-type epitaxial layer 4, N-type and P-type well regions 6 and 5 extending upward from buriedregions 2 and 3 in the N-type epitaxial layer 4, anotherburied region 2 heavily doped with N-type impurity in the boundarybetween the P-type semiconductor substrate land the N-type epitaxial layer 4, and silicon dioxide boundaries 7 on the N-type epitaxial layer 4 to define first areas lying on the well regions 5 and 6 allotted to two complementary MOS transistors to be formed and a second area lying above the buried region 2 allotted to a bipolar transistor to be formed. In the second area the first and second subareas, in which the collector and the base regions of the bipolar transistor are to be formed, are separated and defined by silicon dioxide boundary 7A.
Referring to FIG. 1B, a gate silicon dioxide film 8 is formed on the surface of the epitaxial layer 4. Then, a polycrystalline silicon coating which is 4,000 to 6,000 angstroms thick, is formed on the insulating film 8. The polycrystalline silicon coating thus formed is selectively removed by etching to leave a piece of polycrystalline silicon coating 9 on each of the first areas in which a PMOS device and an NMOS device are to be formed. These pieces of polycrystalline silicon coating 9 are covered by an insulating film of silicon dioxide.
Referring to FIG. 1C, photoresist coating 11A is applied to the adjacent first areas and the first subarea of the second area, and then the second subarea of the second area is injected with a P-type impurity such as boron in the form of ions, thus forming a P-type base region 12.
Referring to FIG. 1D, another photoresist coating 11b is applied to one of the adjacent first area and the second subarea of the second area, exposing the other first area in which an NMOS transistor is to be formed and the first subarea of the second area in which the collector of the bipolar transistor is to be formed. Then, the exposed areas are subjected to ion-injection of an N-type impurity such as arsenic to form N.sup.+ -type source and drain regions 13 in the other first area which is allotted to the NMOS device, and N.sup.+ -type collector region 14 in the second area which is allotted to the bipolar transistor.
Referring to FIG. 1E, still another photoresist coating 11c is applied to the other first area and the first subarea and the proximal part of the second subarea of the second area, exposing the one first area in which the PMOS transistor is to be formed and the distal part of the second subarea of the second area in which the graft base region of the bipolar transistor is to be formed. Then, the exposed area are subjected to ion-injection of a P-type impurity such as boron to form P.sup.+ -type source and drain regions 15 of the PMOS device and P.sup.+ -type graft base region 16 of the bipolar transistor.
Referring to FIG. 1F, a silicon dioxide film 17 is formed on the whole surface of the semiconductor substrate, and holes are made in the part of the insulating film 17 under which part there lie the part of the subsecond area to be allotted to the emitter of the bipolar transistor. The hole is filled with polycrystalline silicon as indicated at 18. An N.sup.+ -emitter region 19 is formed by ion injecting the emitter-allotted part of the subsecond area with an N-type impurity such as arsenic. Finally, a PSG film 20 is formed on the whole surface of the substrate, and holes are made to reach the respective regions 12 to 16, and aluminum electrodes 21 are inserted in these holes.
As described earlier, the N.sup.+ -type-collector region 14 and the P.sup.+ -type-base region 12 of the bipolar transistor are separated by silicon dioxide boundary 7A, thus preventing the lowering of the resistance to counter voltage at the collector-and-base junction the bipolar transistor. With this arrangement the lateral dimension of the silicon dioxide boundary 7A determines the space between the P-type base region 12 and the N type collector region 14 of the bipolar transistor.
In the course of selective oxidization of the epitaxial layer 4 to form silicon dioxide boundary 7A, a certain stress due to such selective oxidization is most likely to appear in the collector-and-base junction to cause a lattice defect, which is a cause for lowering the breakdown voltage at the junction. This will lead to substantial reduction of the output rate of composite semiconductor devices.